Semiconductor device and diagnostic method thereof

ABSTRACT

A semiconductor device includes a test target circuit subjected to self-diagnosis, a PLL circuit that outputs a clock for the self-diagnosis to the test target circuit, a diagnostic register that stores a clock frequency corresponding to an operation speed limit of the test target circuit, and a control circuit that sets a frequency of the clock output from the clock circuit based on the clock frequency stored in the diagnostic register when executing the self-diagnosis.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2010-25153 filed onFeb. 8, 2010 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

1. Field of the Invention

The present invention relates to a semiconductor device, and adiagnostic method thereof, and more particularly, the present inventionrelates to a semiconductor device with a self-diagnostic function and adiagnostic method thereof.

2. Description of the Related Art

Recently, a microcomputer with a self-diagnostic function has beenemployed. The microcomputer executes the self-diagnosis of functionalblocks. For example, the self-diagnosis is executed when supplying powerto the semiconductor device to ensure detection of the microcomputer'sfailure.

Japanese Unexamined Patent Publication No. 2003-68865 discloses theself-diagnostic method using a Built In Self Test (BIST) circuit.Specifically, the self-diagnostic method disclosed in JapaneseUnexamined Patent Publication No. 2003-68865 uses a BIST controller fortransmitting diagnostic conditions, based on which respective functionalblocks are diagnosed.

SUMMARY

There is the following problem in the self-diagnostic method asdisclosed in Japanese Unexamined Patent Publication No. 2003-68865. Thatis, the self-diagnosis is executed at a predetermined operationfrequency in the above-disclosed self-diagnostic method, which may causemisjudgment that the device with operation margin is normally operatedeven if it has been deteriorated since the shipment. If thedeterioration is within the operation margin, the device will be judgedas being normally operated, and accordingly, it is difficult for theabove-disclosed diagnostic method to execute appropriate diagnosis.

The present invention seeks to solve one or more of the above problems,or to improve upon those problems at least in part.

The present invention provides a semiconductor device which includes atarget circuit subjected to self-diagnosis, a clock circuit that outputsa clock for the self-diagnosis to the target circuit, a data storageunit that stores a clock frequency corresponding to an operation speedlimit of the target circuit, and a control unit that sets a frequency ofthe clock output from the clock circuit when executing theself-diagnosis based on the clock frequency stored in the data storageunit. The aforementioned structure allows the diagnosis at the clockfrequency corresponding to the operation speed limit, resulting inappropriate diagnosis.

The present invention provides a method of diagnosing a semiconductordevice. The method includes setting a clock frequency corresponding toan operation speed limit of a target circuit subjected toself-diagnosis, and diagnosing the target circuit using a clock signalat the clock frequency corresponding to the operation speed limit. Themethod allows the diagnosis at the clock frequency corresponding to theoperation speed limit, resulting in appropriate diagnosis.

The present invention provides the semiconductor device capable ofexecuting the diagnosis appropriately and the diagnostic method thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other purposes, advantages and features of the presentinvention will become more apparent from the following description ofcertain exemplary embodiments taken in conjunction with the accompanyingdrawings in which:

FIG. 1 is a block diagram illustrating a structure of a semiconductordevice according to a first exemplary embodiment of the presentinvention;

FIG. 2 is a flowchart of a setting process at shipment in a diagnosticmethod of the semiconductor device according to the first exemplaryembodiment of the present invention;

FIG. 3 is a flowchart representing the diagnostic method of thesemiconductor device according to the first exemplary embodiment of thepresent invention;

FIG. 4 is an explanatory view of a circuit operation of a register;

FIG. 5 is a block diagram illustrating a structure of a semiconductordevice according to a second exemplary embodiment of the presentinvention; and

FIG. 6 is a flowchart representing a diagnostic method of thesemiconductor device according to the second exemplary embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Exemplary Embodiments according to the present invention will bedescribed in detail referring to the drawings. For clear understandingof the explanation, the following description and the drawings arearbitrarily simplified.

First Exemplary Embodiment

A semiconductor device according to a first exemplary embodiment of thepresent invention will be described referring to FIG. 1. FIG. 1 is ablock diagram illustrating a circuit structure of a microcomputer as thesemiconductor device according to the first exemplary embodiment. Amicrocomputer 10 shown in FIG. 1 includes a self-diagnostic function.That is, the microcomputer 10 is realized by a semiconductor chip withthe self-diagnostic function. For example, when power is supplied, themicrocomputer 10 executes the self-diagnosis to determine whether or notfailure has occurred. In this way, the microcomputer 10 is structured asan Integrated Circuit (IC) with the self-diagnostic function. Themicrocomputer 10 may be formed as a BIST circuit.

The microcomputer 10 includes a CPU 11, a general-purpose register 12, aflash memory 13, a control circuit 14, a normal operation register 15, adiagnostic register 16, a selector 17, a PLL circuit 18, and a testtarget circuit 19.

The test target circuit 19 is a functional block subjected to theself-diagnosis. For example, the test target circuit 19 is subjected tothe self-diagnosis when starting the microcomputer 10. After theself-diagnosis of the test target circuit 19, it is normally operated.The test target circuit 19 is designed to perform the predeterminedfunction in a non-diagnostic state where the self-diagnosis is notexecuted. Referring to FIG. 1, one test target circuit 19 is built inthe microcomputer 10. However, two or more test target circuits 19 maybe used as the respective functional blocks. That is, two or morefunctional blocks may be built in the microcomputer 10, each of which issubjected to the diagnosis as the individual test target circuit 19.

In execution of the self-diagnosis, diagnostic data is input into thetest target circuit 19, for example. An actual output valuecorresponding to the input data is compared with an estimated valuecorresponding to the input. That is, the output value corresponding tothe input data in the normal state is set as the estimated value. Thediagnosis is executed by determining whether or not the estimated valueis equal to the actual output value. If the actual output valuecoincides with the estimated value, it is determined that the testtarget circuit 19 normally functions. If the actual output value doesnot coincide with the estimated value, it is determined that the testtarget circuit 19 abnormally functions.

The PLL circuit 18 supplies a clock to the test target circuit 19 byexecuting a PLL (Phase Locked Loop) operation. That is, a signal servingas a reference frequency is input into the PLL circuit 18. The PLLcircuit 18 then outputs a clock signal in synchronization with thesignal as the reference frequency. In this way, the PLL circuit 18becomes a clock circuit for generating the clock.

The test target circuit 19 is operated based on the clock signalsupplied from the PLL circuit 18. The self-diagnosis is executed basedon the clock supplied from the PLL circuit 18. It is then determinedwhether or not the test target circuit 19 has been deteriorated. In anon-diagnostic state, the normal operation is performed based on theclock signal supplied from the PLL circuit 18. The test target circuit19 as the functional block performs the designed function, andaccordingly, it is normally operated. The PLL circuit 18 includes amultiplying factor setting terminal. In accordance with the signal inputinto the multiplying factor setting terminal, the multiplying factorwith respect to the reference frequency is set. According to the firstexemplary embodiment, the multiplying factor varies depending on thediagnostic state and the normal operation (non-diagnostic) state. Thatis, based on the signal input into the multiplying factor settingterminal, the PLL circuit 18 outputs the different clock frequency. ThePLL circuit 18 generates the clock at the frequency in accordance withthe usage so as to be output to the test target circuit 19.

The CPU 11 executes arithmetic processing for operating themicrocomputer 10 by controlling the memory and the functional block.This allows the microcomputer 10 to perform the predetermined operation.For example, the CPU 11 executes the arithmetic processing for runningthe program stored in the flash memory 13. The CPU 11 outputs thearithmetic result to the test target circuit 19, which is the functionalblock. In normal operation, the functional block executes thepredetermined processing.

The general-purpose register 12 stores the normal operation frequencyand the like, and further the value corresponding to the clock frequencyin the normal operation (non-diagnostic) state. Specifically, themultiplying factor corresponding to the clock frequency in the normaloperation state is stored in the general-purpose register 12. It isassumed that the clock frequency in the normal operation(non-diagnostic) state is defined as a normal operation clock frequency.The general-purpose register 12 stores the multiplying factorscorresponding to the normal operation clock frequency and the referencefrequency, respectively. It is assumed that the multiplying factorcorresponding to the normal operation clock frequency is defined as anormal operation multiplying factor. The normal operation multiplyingfactor stored in the general-purpose register 12 may be used for settingnot only the clock frequency in the test target circuit 19 but also theclock frequency for another functional block. The normal operation clockfrequency stored in the general-purpose register 12 is stored in thenormal operation register 15. The general-purpose register 12 may bebuilt in the CPU 11.

The flash memory 13 is nonvolatile, and stores program and data forallowing the microcomputer 10 to execute predetermined operations. Theprogram and data stored in the flash memory 13 are read by the CPU 11.The flash memory 13 stores setting data for setting the clock frequencyin diagnosis (diagnostic clock frequency). For example, the flash memory13 has a region set for storing the diagnostic clock frequency. Theflash memory 13 includes a data output terminal for outputting thesetting data. The diagnostic clock frequency stored in the flash memory13 is stored in the diagnostic register 16. Specifically, the flashmemory 13 has the region set for storing the multiplying factorcorresponding to the diagnostic clock frequency. The flash memory 13outputs the multiplying factor to the diagnostic register 16. Thediagnostic register 16 stores the multiplying factor (hereinafterreferred to as the diagnostic multiplying factor) corresponding to thediagnostic clock frequency.

The selector 17 selects one of a clock frequency from the normaloperation clock frequency stored in the normal operation register 15 andthe diagnostic clock frequency stored in the diagnostic register 16. Theselector 17 outputs the selected clock frequency to the PLL circuit 18.Specifically, the selector 17 selects one of the multiplying factor forthe normal operation stored in the normal operation register 15 and themultiplying factor for diagnosis stored in the diagnostic register 16.The selected multiplying factor is output to the multiplying factorsetting terminal of the PLL circuit 18.

The control circuit 14 controls selection operations performed by theselector 17. The control circuit 14 outputs a self-diagnosis mode signalfor executing the self-diagnosis. Upon reception of the self-diagnosismode signal output from the control circuit 14, the selector 17 selectsan appropriate multiplying factor so as to be output to the PLL circuit18. That is, in accordance with the self-diagnosis mode signal, theselector 17 selects one of the diagnostic multiplying factor and thenormal operation multiplying factor, and outputs the selectedmultiplying factor to the multiplying factor setting terminal of the PLLcircuit 18. Based on the self-diagnosis mode, one of the self-diagnosismode for executing the self-diagnosis and the normal operation mode forexecuting the normal operation is selected.

The control circuit 14 further controls setting of the diagnosticmultiplying factor for each IC chip, for example. Specifically, thesuitable diagnostic multiplying factor is measured for each chip atshipment of the respective chips. The clock frequency corresponding tothe operation speed limit is detected for each chip, and theself-diagnosis is executed at the detected clock frequency, resulting ineven more appropriate diagnosis.

The value of the diagnostic multiplying factor is different from that ofthe normal operation multiplying factor. Specifically, the diagnosticmultiplying factor is set to be larger than the normal operationmultiplying factor. This makes it possible to detect the deterioratedstate of the microcomputer 10 before its failure. In other words, as thevalue of the diagnostic multiplying factor is large, abnormality may bedetected before the failure in spite of the operation margin of theclock frequency for normally operating the microcomputer 10. That is,deterioration can be detected before reveal of the operation abnormalityat the operation speed in the normal operation mode.

Referring to FIG. 2, the diagnostic method according to the firstexemplary embodiment will be described. FIG. 2 is a flowchartrepresenting the process for setting the multiplying factor in thediagnostic method. The process shown in FIG. 2 is executed for each chipat shipment thereof, for example. This makes it possible to set theoptimum multiplying factor for each chip. That is, the process shown inFIG. 2 is executed for setting the clock frequency corresponding to theoperation speed limit for each chip. The clock frequency correspondingto the operation speed limit is set as the diagnostic clock frequency.

In step S101, “0” is input into the general-purpose register 12. Then instep S102, the value in the general-purpose register 12 is input intothe normal operation register 15 which receives the input value of “0”.This value corresponds to the multiplying factor of 1, that is, thereference frequency. In step S103, the self-diagnosis is executed, andthe reference frequency is input into the test target circuit 19 fromthe PLL circuit 18. The test target circuit 19 executes the diagnosis atthe reference frequency. The diagnostic data is input into the testtarget circuit 19. Then the output of the diagnostic data and theestimated value are compared. At this time, the test target circuit 19executes the diagnostic operation at the reference frequency.

Based on the self-diagnostic result, it is determined whether or not thetest target circuit 19 is normally operated in step S104. That is, theoutput value corresponding to the input diagnostic data and theestimated value are compared. If the output value coincides with theestimated value, that is, the output has the designed value, it isdetermined that the test target circuit 19 has been normally operated atthe clock frequency, and PASS is obtained. If the output value does notcoincide with the estimated value, that is, the output does not have thedesigned value, it is determined that the test target circuit 19 has notbeen normally operated at the clock frequency, and FAIL is obtained.

If PASS is obtained, the value in the general-purpose register 12 isincremented in step S105. Then the value in the general-purpose register12 is incremented by 1. The process returns to step S102 where the sameprocessing (steps S103, S104) is executed. That is, the diagnosticprocess is executed by increasing the multiplying factor of the clockfrequency. Then self-diagnosis of the test target circuit 19 is executedat the frequency higher than the clock frequency determined as PASS. Thevalue in the general-purpose register 12 is incremented until FAIL isobtained. That is, the multiplying factor is gradually increased untilthe test target circuit 19 is no longer normally operated.

If FAIL is obtained, the value in the general-purpose register 12 isdecremented by 1 in step S106. Then the decremented value is written inthe flash memory 13 in step S107. The highest multiplying factordetermined as PASS is written in the flash memory 13. The highestmultiplying factor becomes the one corresponding to the clock frequencyat the operation speed limit. That is, the multiplying factorcorresponding to the diagnostic clock frequency is stored in the flashmemory 13. When the diagnostic clock frequency is determined, theshipment is ready. In this way, the multiplying factor corresponding tothe operation speed limit may be measured for each chip.

A diagnostic operation after shipment will be described referring toFIG. 3. FIG. 3 is a flowchart representing the diagnostic processing. Instep S201, the self-diagnostic function is activated upon start of themicrocomputer 10. Then the control circuit 14 reads the diagnosticmultiplying factor stored in the flash memory 13 in step S202, and thevalue is set in the diagnostic register 16 in step S203. Then themultiplying factor corresponding to the clock frequency at the operationspeed limit set in the flow at shipment is stored in the diagnosticregister 16. The self-diagnosis is then started in step S204. The PLLcircuit 18 outputs the diagnostic clock frequency to the test targetcircuit 19. That is, the selector 17 selects the diagnostic multiplyingfactor in accordance with the self-diagnosis mode signal from thecontrol circuit 14, as shown in FIG. 1. Accordingly, the diagnosticmultiplying factor is input into the multiplying factor setting terminalof the PLL circuit 18. The PLL circuit 18 then outputs the clock signalat the diagnostic clock frequency to the test target circuit 19.

When the self-diagnosis is finished in step S205, the determination ismade in step S206 with respect to PASS/FAIL based on the result. If PASSis obtained as a determination result of the self-diagnosis, it isdetermined that the subject device is normally operated. If FAIL isobtained as the determination result of the self-diagnosis, it isdetermined that the subject device has been in a deteriorated state. Inspite of the clock frequency determined as PASS at the shipment, thesubject device has been deteriorated as it is used, and may bedetermined as FAIL. This makes it possible to detect the deterioratedstate before the failure. That is, the determination may be made withrespect to the deteriorated state of the subject device before itbecomes inoperative at the normal operation clock frequency. Thedeterioration before failure may be detected so as to appropriatelydiagnose the test target circuit 19.

The timing for writing data in the diagnostic register 16 will bedescribed referring to FIG. 4. FIG. 4 represents a circuit diagram and atiming chart for explaining the writing operation in the diagnosticregister 16. Referring to FIG. 4, the circuit diagram is shown at theupper side and the timing chart is shown at the lower side. FIG. 4illustrates an example of the 8-bit operation of the diagnostic register16. Input data DIN output from the data output terminal of the flashmemory 13 is written in the diagnostic register 16 in accordance with awrite enable signal WR_enable from the control circuit 14. The value ofthe input data DIN having the write enable signal WR_enable output at atiming H is written in the diagnostic register 16. The data written inthe diagnostic register 16 is output to the selector 17 as output dataDOUT. As the process for writing in the normal operation register 15 isthe same as the one for the diagnostic register 16, and explanation ofthe process will be omitted. The write enable signal WR_enable from theCPU 11 or the general-purpose register 12 and the input data DIN areinput into the normal operation register 15.

The control circuit 14 built in the chip reads the multiplying factor ofthe built-in flash memory 13 before executing the self-diagnosis, andthe read multiplying factor is stored in the diagnostic register 16. Themultiplying factor data stored in the diagnostic register 16 is selectedupon start-up of the self-diagnosis mode, and supplied to themultiplying factor setting terminal of the PLL circuit 18. Theself-diagnosis is executed at the clock frequency with the suppliedmultiplying factor. The failure owing to deterioration which occursafter prolonged use of the product may be detected beforehand at thestage where the system operation is ensured. This makes it possible tomaintain the system in safe state. Detection with respect to increase inthe current owing to failure may also be improved. The deterioratedstate may be detected just before breakage of the element owing tofailure, thus preventing short-circuit caused by the failure.

Second Exemplary Embodiment

A semiconductor device according to a second exemplary embodiment willbe described referring to FIG. 5. FIG. 5 is a block diagram illustratinga structure of the microcomputer 10 as the semiconductor deviceaccording to the second exemplary embodiment. The microcomputer 10illustrated in FIG. 5 has substantially the same basic structure as thatof the microcomputer 10 according to the first exemplary embodiment. Inthe second exemplary embodiment, explanation of the components common tothose of the first exemplary embodiment will be omitted.

The second exemplary embodiment is formed by adding a selector 20 and anOR circuit 21 to the structure of the microcomputer 10 according to thefirst exemplary embodiment. The control circuit 14 outputs twoself-diagnosis mode signals. It is assumed that one of the twoself-diagnosis mode signals is set as a self-diagnosis mode signal 1 andthe other is set as a self-diagnosis mode signal 2. The rest of thestructure is the same as the first exemplary embodiment, and explanationthereof, thus will be omitted.

Like the first exemplary embodiment, the self-diagnosis mode signal 1 isused for executing the self-diagnostic test at the operation speed limitfrequency. This mode is defined as a self-diagnosis mode 1. Meanwhile,the self-diagnosis mode signal 2 is used for executing theself-diagnostic test at the normal operation frequency. This mode isdefined as a self-diagnosis mode 2. For example, if the self-diagnostictest is conducted at the operation speed limit frequency, theself-diagnosis mode signal 1 is set as H, and the self-diagnosis modesignal 2 is set as L. Meanwhile, if the self-diagnostic test isconducted at the normal operation frequency, the self-diagnosis modesignal 1 is set as L, and the self-diagnosis mode signal 2 is set as H.In the non-diagnostic state where the self-diagnosis is not executed,that is, in the normal operation state, both the self-diagnosis modesignals 1 and 2 are set as L.

When executing the self-diagnosis as described above, the controlcircuit 14 outputs the self-diagnosis mode signal 1 or theself-diagnosis mode signal 2. The self-diagnosis mode signal 1 from thecontrol circuit 14 is input into the selector 20. The selector 20receives input values of the multiplying factors from the normaloperation register 15 and the diagnostic register 16, respectively. Theselector 20 outputs the multiplying factor corresponding to theoperation speed limit frequency from the diagnostic register 16 when theself-diagnosis mode signal 1 is set as H, and outputs the multiplyingfactor corresponding to the normal operation frequency from the normaloperation register 15 when the self-diagnosis mode signal 1 is set as L.The multiplying factor from the selector 20 is input into the selector17.

The self-diagnosis mode signals 1 and 2 from the control circuit 14 areinput into the OR circuit 21. If at least one of the self-diagnosis modesignals 1 and 2 is set as H, the OR circuit 21 outputs the signal H tothe selector 17. If both the self-diagnosis mode signals 1 and 2 are setas L, the OR circuit 21 outputs the signal L to the selector 17. Theselector 17 receives inputs of the multiplying factors from the selector20 and the multiplying factor from the normal operation register 15.When the signal from the OR circuit 21 is set as H, the selector 17outputs the multiplying factor from the selector 20 to the PLL circuit18. Then the PLL circuit 18 is operated at the multiplying factor forthe diagnosis. That is, the clock is set at the operation limit speedfrequency or the normal operation frequency so as to execute theself-diagnosis appropriately. When the signal from the OR circuit 21 isset as L, the selector 17 outputs the multiplying factor from the normaloperation register 15 to the PLL circuit 18. That is, the clock is setat the normal operation frequency.

The self-diagnostic method according to the second exemplary embodimentwill be described referring to FIG. 6. FIG. 6 is a flowchartrepresenting the diagnostic procedure. In the second exemplaryembodiment, explanation of the same process as that of the firstexemplary embodiment will be omitted. Setting of the operation limitspeed frequency upon shipment is the same as represented by the flow ofthe first exemplary embodiment represented by FIG. 2.

The self-diagnosis mode 1 is started using the self-diagnosis modesignal 1 in step S301 for executing the diagnosis at the operation limitspeed frequency. Then the multiplying factor is read from the flashmemory 13 in step S302. In step S303, the control circuit 14 sets theread multiplying factor in the diagnostic register 16. In theaforementioned state, the self-diagnosis is started in step S304. Theself-diagnosis is executed at the operation limit speed frequency. Instep S305, the self-diagnosis is finished. The determination withrespect to PASS/FAIL is executed in step S306. That is, the estimatedvalue and the output value with respect to the diagnostic data arecompared. If the estimated value coincides with the output value, PASSis obtained, and it is determined as being normal. In this case, thedevice is operated at the operation limit speed with no problem. Thedevice has hardly been deteriorated since the shipment, and it isdetermined that the device is normally operated.

If FAIL is obtained, the self-diagnosis mode 2 is started using theself-diagnosis mode signal 2 in step S307 for executing the diagnosis atthe normal operation frequency. Then the normal operation register 15 isinitialized. This allows the general-purpose register 12 to write thenormal operation frequency in the normal operation register 15. In theaforementioned state, the self-diagnosis is started in step S309. Theself-diagnosis is executed at the normal operation frequency. When theself-diagnosis is finished in step S310, the PASS/FAIL determination ismade in step S311. That is, the estimated value and the output valuewith respect to the diagnostic data are compared. If the estimated valuecoincides with the output value, PASS is obtained as the determinationresult. In this case, it is determined that the test target circuit 19is in the deteriorated state. That is, the subject device cannot benormally operated at the operation limit speed, but it is normallyoperated at the normal operation speed. It is determined that thesubject device has been in the deteriorated state since the shipment,which is within the operation margin. It is therefore determined as inthe deteriorated state. Meanwhile, if the estimated value does notcoincide with the output value, FAIL is obtained as the determinationresult. In this case, it is determined that failure has occurred in thetest target circuit 19. That is, it cannot be normally operated at thenormal operation frequency, and therefore, the test target circuit 19 isdetermined as having failure.

Execution of the self-diagnosis ensures detection of the deterioratedstate before the failure, thus allowing the appropriate action to betaken to the deteriorated functional block. That is, the action may betaken to the block in the deteriorated state before the failure,resulting in improved reliability.

In the second exemplary embodiment, two clock frequency values are usedfor executing the diagnosis. However, three or more clock frequencyvalues may be used for executing the diagnosis. For example, theoperation speed limit frequency, the normal operation frequency, and afrequency therebetween may be used. Specifically, three values of themultiplying factor are set so that one of them is selected based on theself-diagnosis mode signals 1 to 3. This makes it possible to determinewith respect to the normally operable frequency in stages, thusdetecting advancement of deterioration.

Other Exemplary Embodiments

In the first and the second exemplary embodiments, the multiplyingfactor corresponding to the clock frequency is stored in the respectiveregisters. The value of the clock frequency may be directly stored.Alternatively, each register may be structured to store the valuecorresponding to the clock frequency. That is, the value other than themultiplying factor may be stored in the flash memory 13 for the purposeof storing the diagnostic clock frequency corresponding to the operationspeed limit. The frequency or the multiplying factor may be stored in amemory unit other than the register. The general-purpose register 12 andthe normal operation register 15 are separately provided. However, thesame register may be used.

The frequency corresponding to the operation limit speed is measuredbefore shipment. The frequency measured for each chip is stored in theflash memory 13 built in the chip. This makes it possible to executeappropriate diagnosis in spite of each difference among the devices. Inother words, this makes it possible to execute appropriate diagnosis foreach chip.

Although the invention has been described above in connection withseveral exemplary embodiments thereof, it will be appreciated by thoseskilled in the art that those exemplary embodiments are provided solelyfor illustrating the invention, and should not be relied upon toconstrue the appended claims in a limiting sense.

Further, it is noted that, notwithstanding any claim amendments madehereafter, applicant's intent is to encompass equivalents all claimelements, even if amended later during prosecution.

1. A semiconductor device comprising: a target circuit subjected toself-diagnosis; a clock circuit that outputs a clock for theself-diagnosis to the target circuit; a data storage unit that stores aclock frequency corresponding to an operation speed limit of the targetcircuit; and a control unit that sets a frequency of the clock outputfrom the clock circuit when executing the self-diagnosis based on theclock frequency stored in the data storage unit.
 2. The semiconductordevice according to claim 1, wherein the target circuit is normallyoperated in a non-diagnostic state at a clock frequency lower than theclock frequency stored in the data storage unit.
 3. The semiconductordevice according to claim 1, wherein the clock circuit is a PLL circuit,and wherein the data storage unit stores a multiplying factor of the PLLcircuit.
 4. The semiconductor device according to claim 1, wherein thedata storage unit stores two or more frequency values for executing theself-diagnosis.
 5. A method of diagnosing a semiconductor devicecomprising: setting a clock frequency corresponding to an operationspeed limit of a target circuit subjected to self-diagnosis; anddiagnosing the target circuit using a clock signal at the clockfrequency corresponding to the operation speed limit.
 6. The methodaccording to claim 5, wherein the target circuit is normally operated ina non-diagnostic state at a clock frequency lower than the clockfrequency corresponding to the operation speed limit.
 7. The methodaccording to claim 5, wherein a multiplying factor of the clockfrequency corresponding to the operation speed limit is set, and whereina clock of the frequency corresponding to the operation limit speed issupplied to the target circuit by supplying the multiplying factor to aPLL circuit for generating the clock.
 8. The method according to claim5, wherein diagnosis is executed by changing a frequency for theself-diagnosis.
 9. The method according to claim 5, wherein the clockfrequency corresponding to the operation limit speed is measured beforeshipment of the semiconductor device, and wherein the diagnosis isexecuted at the clock frequency corresponding to the operation limitspeed after the shipment to detect deterioration of the semiconductordevice after the shipment.